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Disambiguation of "Seo, Dongwook"

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A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology.

, , , , , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Dongwook Park

Eunyoung Seo

Ean-Jeong Seo

Paek Pyung Seon

Bong-Seock Seo

 

Other publications of authors with the same name

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology., , , , , , , , , and 1 other author(s). CICC, page 1-7. IEEE, (2022)Real-time flood detection for video surveillance., , , , and . IECON, page 4082-4085. IEEE, (2015)Laser scanner based heading angle and distance estimation., , , and . ICIT, page 1718-1722. IEEE, (2015)A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology., , , , , , , , , and 9 other author(s). ISSCC, page 392-394. IEEE, (2019)4nm Voltage Auto-Tracking SRAM Pulse Generator with Fully RC Optimized Row Auto-Tracking Write Assist Circuits., , , , and . VLSI Technology and Circuits, page 218-219. IEEE, (2022)Multi-layer superpixel-based MeshStereo for accurate stereo matching., and . HSI, page 242-245. IEEE, (2017)5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application., , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology., , , , , , , , , and 3 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Building detection based on facet for urban reconstruction., , , and . IECON, page 2864-2867. IEEE, (2015)Lane marking recognition based on laser scanning., , , and . ISIE, page 962-965. IEEE, (2015)