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Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis., , and . ISOCC, page 203-206. IEEE, (2021)Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs., , , and . ISLPED, page 26:1-26:6. ACM, (2022)Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs., , , , , and . ETS, page 1-6. IEEE, (2019)Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (7): 1944-1956 (July 2024)Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees., and . ICCAD, page 691-696. IEEE, (2013)Timing-Aware Tier Partitioning for 3D ICs with Critical Path Consideration., and . ICEIC, page 1-4. IEEE, (2024)Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology., , , , , and . ISOCC, page 215-218. IEEE, (2021)Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement., , , and . MWSCAS, page 232-235. IEEE, (2021)Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse., , , , , , , , , and 5 other author(s). DAC, page 178. ACM, (2019)Synthesizing Asynchronous Circuits toward Practical Use., and . ISVLSI, page 47-52. IEEE Computer Society, (2016)