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Disambiguation of "Shannon, Lesley"

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DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization.

, , , and . ISQED, page 1-7. IEEE, (2024)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Lesley Mearns

Lesley Bissland

Shannon Ryan

Mark Shannon

Harry Shannon

 

Other publications of authors with the same name

A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only)., , and . FPGA, page 242. ACM, (2014)Using reconfigurability to achieve real-time profiling for hardware/software codesign., and . FPGA, page 190-199. ACM, (2004)The routability of multiprocessor network topologies in FPGAs., , and . SLIP, page 49-56. ACM, (2006)An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs., and . FPT, page 361-364. IEEE, (2008)A Multiprocessor System-on-Chip Implementation of a Laser-based Transparency Meter on an FPGA., , , and . FPT, page 373-376. IEEE, (2007)Standardizing the Performance Assessment of Reconfigurable Processor Architectures., and . FCCM, page 282-283. IEEE Computer Society, (2003)Boosting Multiple Multipliers Packing on FPGA DSP Blocks via Truncation and Compensation-based Approximation., , , and . ISVLSI, page 222-227. IEEE, (2024)LEAP: A Deep Learning based Aging-Aware Architecture Exploration Framework for FPGAs., , , and . FPGA, page 146. ACM, (2021)Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support., , and . FPL, page 224-230. IEEE, (2012)A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification., , , , , and . FPL, page 1-6. IEEE, (2006)