( en | de | ru )

 

Disambiguation of "Carpenter, Gary D."

Author of the publication

copydeleteadd this publication to your clipboard
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs.

, , and . ICCD, page 134-139. IEEE Computer Society, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Alexander Gary

Klaus Gary

Regina Gary

Bente Gary

Max Gary

 

Other publications of authors with the same name

Experience with building a commodity Intel-based ccNUMA system., , , , , , , , , and 5 other author(s). IBM J. Res. Dev., 45 (2): 207-228 (2001)A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling., , , , , , , and . IEEE J. Solid State Circuits, 37 (11): 1441-1447 (2002)A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor., , , , , , , , and . ISSCC, page 398-399. IEEE, (2007)The design and application of the PowerPC 405LP energy-efficient system-on-a-chip., , and . IBM J. Res. Dev., 47 (5-6): 631-640 (2003)Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs., , and . ICCD, page 134-139. IEEE Computer Society, (2003)A Scheme for On-Chip Timing Characterization., , , and . VTS, page 24-29. IEEE Computer Society, (2006)An on-chip dual supply charge pump system for 45nm PD SOI eDRAM., , , , , , , , , and 3 other author(s). ESSCIRC, page 66-69. IEEE, (2008)On-Chip Delay Measurement Based Response Analysis for Timing Characterization., , , , , and . J. Electron. Test., 26 (6): 599-619 (2010)