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Multiple Si layer ICs: motivation, performance analysis, and design implications., , , and . DAC, page 213-220. ACM, (2000)Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects., and . DAC, page 798-803. ACM, (2001)Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs., , and . DAC, page 250-255. ACM, (2008)Exploration and Exploitation of Strain Engineering in 2D-FETs., , , , and . DRC, page 1-2. IEEE, (2023)A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs., , and . ICCD, page 411-416. IEEE Computer Society, (2005)Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits., , and . ISQED, page 346-351. IEEE Computer Society, (2005)Plenary Session 2P., and . ISQED, page 461. IEEE Computer Society, (2005)Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture., , , , , , , , and . ISQED, page 496-501. IEEE Computer Society, (2002)Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design., , and . ICCAD, page 714-720. IEEE, (2010)Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design., , and . ICCAD, page 270-277. IEEE Computer Society, (2008)