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Disambiguation of "Cervero, Teresa"

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b8c: SpMV accelerator implementation leveraging high memory bandwidth.

, , , , , and . FCCM, page 216. IEEE, (2023)

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Teresa Edenfeld

Charakterisierung der Funktion der Proteinkinase D2 als Regulator der Chromogranin-A-Sekretion in humanen BON neuroendokrinen Tumorzellen. Uni Ulm, (2010)

Teresa Carlomagno

Teresa Halsband

Teresa Schaumann

Teresa Gaillard

 

Other publications of authors with the same name

Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs., , , , , , and . RAPIDO@HiPEAC, page 29-34. ACM, (2024)Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress., , , , , , , , and . ISC Workshops, volume 13999 of Lecture Notes in Computer Science, page 472-485. Springer, (2023)Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach., , , , , and . FPL, page 151-158. IEEE, (2023)A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems., , , and . ARC, volume 7199 of Lecture Notes in Computer Science, page 314-319. Springer, (2012)Scalable Models for Autonomous Self-Assembled Reconfigurable Systems., , , , and . ReConFig, page 410-415. IEEE Computer Society, (2011)Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs., , , , , , and . FPL, page 369-375. IEEE Computer Society, (2011)b8c: SpMV accelerator implementation leveraging high memory bandwidth., , , , , and . FCCM, page 216. IEEE, (2023)Ethernet Emulation over PCIe for RISC-V Software Development Vehicles., , , , , , and . DCIS, page 1-6. IEEE, (2023)Scalable architectures for real-time hyperspectral unmixing., , , , and . Microelectron. J., 45 (10): 1292-1303 (2014)A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs., , , , , , and . ICME, page 1-6. IEEE Computer Society, (2011)