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Disambiguation of "Palla, Fabrizio"

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Optical Wireless Systems for High Energy Physics: Design and Characterization.

, , , , , , , , , and . ICTON, page 1-4. IEEE, (2019)

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Ottokar Palla

Murthy Palla

Heinz Palla

Peter Palla

Heike Palla

 

Other publications of authors with the same name

Track finding mezzanine for Level-1 triggering in HL-LHC experiments., , , , , , , , , and 10 other author(s). MOCAST, page 1-4. IEEE, (2017)A low-power and high-density Associative Memory in 28 nm CMOS technology., , , , , , , , , and 3 other author(s). MOCAST, page 1-4. IEEE, (2017)A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications., , , , , , , , , and 7 other author(s). ICECS, page 392-395. IEEE, (2015)Optical Wireless Systems for High Energy Physics: Design and Characterization., , , , , , , , , and . ICTON, page 1-4. IEEE, (2019)Testing a 1 Gbit/s Optical Wireless Communication System against Extreme Space Conditions., , , , , , , , and . WiSEE, page 138-141. IEEE, (2023)10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation Environments., , , , and . ICECS, page 1-4. IEEE, (2023)Characterization of an Associative Memory Chip in 28 nm CMOS Technology., , , , , , , , , and 8 other author(s). ISCAS, page 1-5. IEEE, (2018)Radiation Hardness by Design Techniques for 1 Grad TID Rad-Hard Systems in 65 nm Standard CMOS Technologies., , , and . ApplePies, page 269-276. Springer, (2018)CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments., , , , , , , , , and 32 other author(s). IWASI, page 49-54. IEEE, (2015)A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications., , , , and . IEEE Access, (2023)