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An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.

, , , , , , , , and . IEEE Trans. Computers, 72 (1): 222-235 (2023)

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Scalable Model Checking Beyond Safety - A Communication Fabric Perspective.. University of California, Berkeley, USA, (2013)NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract)., , , , , , and . BCB, page 623-624. ACM, (2014)Template-based Synthesis of Instruction-Level Abstractions for SoC Verification., , , and . FMCAD, page 160-167. IEEE, (2015)BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies., , and . ASP-DAC, page 366-371. IEEE, (2015)A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis., , and . VLSI Design, page 95-102. IEEE Computer Society, (2007)Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs., , , , and . DAC, page 43. ACM, (2019)Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware., , , , and . DAC, page 91:1-91:6. ACM, (2018)Malware detection using machine learning based analysis of virtual memory access patterns., , , and . DATE, page 169-174. IEEE, (2017)Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK., , , , , , , , , and . DAC, page 1-6. IEEE, (2023)Evaluating the security of logic encryption algorithms., , and . HOST, page 137-143. IEEE Computer Society, (2015)