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Disambiguation of "Cheng, Chung-Kuan"

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New Spectral Linear Placement and Clustering Approach.

, , , and . DAC, page 88-93. ACM Press, (1996)

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Chung-hsin Cheng

Yuan-Chung Cheng

Wen Chung Cheng

Chung-tao Cheng

Cheng Han Chung

 

Other publications of authors with the same name

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform., , , and . IEEE Access, (2022)Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (6): 1178-1191 (2021)Stability and Convergency Exploration of Matrix Exponential Integration on Power Delivery Network Transient Simulation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2735-2748 (2020)Reliability aware through silicon via planning for 3D stacked ICs., , , , , , , and . DATE, page 288-291. IEEE, (2009)Layer minimization in escape routing for staggered-pin-array PCBs., , , and . ASP-DAC, page 187-192. IEEE, (2013)A new layout-driven timing model for incremental layout optimization., , and . ASP-DAC, page 127-131. IEEE, (1997)A multi-level transmission line network approach for multi-giga hertz clock distribution., and . ASP-DAC, page 103-106. ACM Press, (2005)Floorplanning with abutment constraints based on corner block list., , , , , and . Integr., 31 (1): 65-77 (2001)On general zero-skew clock net construction., and . IEEE Trans. Very Large Scale Integr. Syst., 3 (1): 141-146 (1995)Routability improvement using dynamic interconnect architecture., and . IEEE Trans. Very Large Scale Integr. Syst., 6 (3): 498-501 (1998)