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Disambiguation of "Kim, Lee-Sup"

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A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 380-384 (2017)

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Sang Sup Kim

Kwang-Sup Lee

Sang-Sup Lee

Yong-Sup Kim

Lee Jun Kim

 

Other publications of authors with the same name

1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS., and . VLSIC, page 144-145. IEEE, (2012)An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages., and . ISCAS, page 3973-3976. IEEE, (2010)Charge-pump reducing current mismatch in DLLs and PLLs., and . ISCAS, IEEE, (2006)A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator., , and . ISCAS (5), page 373-376. IEEE, (2002)A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme., , and . ISCAS (1), page 461-464. IEEE, (2002)All-digital hybrid temperature sensor network for dense thermal monitoring., , , , , and . ISSCC, page 260-261. IEEE, (2013)A clock delayed sleep mode domino logic for wide dynamic OR gate., and . ISLPED, page 176-179. ACM, (2003)SPAF: Sub-texel Precision Anisotropic Filtering., , and . Workshop on Graphics Hardware, page 99-107. The Eurographics Association, (2001)A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (8): 733-737 (2016)A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (11): 1564-1568 (2018)