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An integrated nonlinear placement framework with congestion and porosity aware buffer planning., , and . DAC, page 702-707. ACM, (2008)X-architecture placement based on effective wire models., , and . ISPD, page 87-94. ACM, (2007)MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs., , , and . ASP-DAC, page 557-562. ACM, (2019)SoC test scheduling using the B-tree based floorplanning technique., , and . ASP-DAC, page 1188-1191. ACM Press, (2005)A novel damped-wave framework for macro placement., , and . ICCAD, page 504-511. IEEE, (2017)MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (9): 1621-1634 (2008)NTUplace2: a hybrid placer using partitioning and analytical techniques., , , , and . ISPD, page 215-217. ACM, (2006)MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs., , , , and . DAC, page 447-452. IEEE, (2007)Double patterning lithography-aware analog placement., , , , and . DAC, page 4:1-4:6. ACM, (2013)Fast analog layout prototyping for nanometer design migration., , , , , and . ICCAD, page 517-522. IEEE Computer Society, (2011)