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A Brief Survey of Fault Tolerant Techniques for Field Programmable Gate Arrays.

, , and . CCWC, page 823-828. IEEE, (2022)

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A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures., and . DFT, page 56-63. IEEE Computer Society, (1993)Detection and Isolation of Faulty Processors in Multiprocessor Systems via TMR-Based Time Redundant Task Scheduling.. CDES, page 42-47. CSREA Press, (2009)Mutation-based validation of high-level microprocessor implementations., and . HLDVT, page 81-86. IEEE Computer Society, (2004)ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits., and . VTS, page 221-230. IEEE Computer Society, (2000)Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling., and . VLSI, page 51-57. CSREA Press, (2003)EGFC: An exact global fault collapsing tool for combinational circuits.. Circuits, Signals, and Systems, page 56-61. IASTED/ACTA Press, (2005)Time-Redundant Logic-Level Protection Mechanisms from Soft Errors in Digital Systems.. CDES, page 17-21. CSREA Press, (2010)Concurrent error correction in iterative circuits by recomputing with partitioning and voting., and . VTS, page 174-177. IEEE Computer Society, (1993)High-level design verification of microprocessors via error modeling., , , , and . ACM Trans. Design Autom. Electr. Syst., 3 (4): 581-599 (1998)A Novel Functional Testing and Verification Technique for Logic Circuits., , and . CDES, page 129-135. CSREA Press, (2005)