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Speculative Register Promotion Using Advanced Load Address Table (ALAT).

, , , and . CGO, page 125-134. IEEE Computer Society, (2003)

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The Performance of a Fault-Tolerant Multistage Interconnection Network., , and . ICPP, page 458-465. IEEE Computer Society Press, (1985)Distributing Hot-Spot Addressing in Large Scale Multiprocessor., , and . ICPP, page 51-58. IEEE Computer Society Press, (1986)Comparing Parallelism Extraction Techniques: Superscalar Processors, Pipelined Processors, and Multiprocessors., and . ICPP (1), page 563-564. Pennsylvania State University Press, (1990)A Synchronization Scheme and Its Applications for Large Multiprocessor Systems., and . ICDCS, page 486-493. IEEE Computer Society, (1984)Interprocedural Analysis for Parallel Programs., and . ICPP (2), page 221-228. Pennsylvania State University Press, (1988)0-271-00654-4.Dynamic Processor Self-Scheduling for General Parallel Nested Loops., , , and . IEEE Trans. Computers, 39 (7): 919-929 (1990)A formally verified transformation to unify multiple nested clocks for a Lustre-like language., , , , , and . Sci. China Inf. Sci., 62 (1): 12801:1-12801:3 (2019)Compiler techniques for data synchronization in nested parallel loops., , and . ICS, page 177-186. ACM, (1990)Program Optimization for Concurrent Multithreaded Architectures., , and . LCPC, volume 1366 of Lecture Notes in Computer Science, page 146-162. Springer, (1997)The superthreaded architecture: thread pipelining with run-time data dependence checking and control speculation., and . IEEE PACT, page 35-46. IEEE Computer Society, (1996)