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A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS.

Y. Lee, T. Huang, K. Chu, C. Chiu, K. Chen, Y. Lin, T. Tsai, C. Yeh, C. Huang, and C. Lee. ESSCIRC, page 161-164. IEEE, (2012)

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Ying Lin

Hsi-Lin Chao

Ying-Tung Lin

Ying Ying

Lin Lin

Other publications of authors with the same name

An enhanced-security buck DC-DC converter with true-random-number-based pseudo hysteresis controller for internet-of-everything (IoE) Devices.W. Yang, L. Chu, S. Yang, Y. Lai, S. Chen, K. Chen, Y. Lin, S. Lin, and T. Tsai. ISSCC, page 126-128. IEEE, (2018)Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology.H. Chen, W. Chen, Y. Chou, M. Chien, C. Wey, K. Chen, Y. Lin, T. Tsai, and C. Lee. CICC, page 1-4. IEEE, (2014)120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs.H. Yang, C. Chiu, S. Lai, J. Chen, C. Chang, C. Meng, K. Chen, C. Wey, Y. Lin, C. Lee and 3 other author(s). ESSCIRC, page 291-294. IEEE, (2015)A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With ά-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control.T. Huang, C. Hsieh, Y. Yang, Y. Lee, Y. Kang, K. Chen, C. Huang, Y. Lin, and M. Lee. IEEE J. Solid State Circuits, 47 (4): 852-862 (2012)Single-Inductor Quad-Output Switching Converter With Priority-Scheduled Program for Fast Transient Response and Unlimited Load Range in 40 nm CMOS Technology.W. Chen, Y. Su, T. Huang, T. Tsai, R. Peng, K. Lin, K. Chen, Y. Lin, C. Lee, S. Lin and 1 other author(s). IEEE J. Solid State Circuits, 50 (7): 1525-1539 (2015)Monolithic GaN-Based Driver and GaN Switch With Diode-Emulated GaN Technique for 50-MHz Operation and Sub-0.2-ns Deadtime Control.T. Wang, Y. Kao, S. Hung, Y. Wen, T. Yang, S. Li, K. Chen, K. Zheng, Y. Lin, S. Lin and 1 other author(s). IEEE J. Solid State Circuits, 57 (12): 3877-3888 (2022)A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration.Y. Lu, S. Liu, Y. Yang, H. Kang, C. Chen, K. Chan, and Y. Lin. IEEE Trans. Circuits Syst. II Express Briefs, 68 (3): 873-877 (2021)A Pre-Charge Tracking Technique in the 40 MHz High-Speed Switching 48-to-5 V GaN-Based DC-DC Buck Converter for Reducing Large Self-Commutation Loss and Achieving a High Efficiency of 95.4%.T. Yang, Y. Wen, C. Chiu, K. Chen, Y. Lin, S. Lin, and T. Tsai. IEEE J. Solid State Circuits, 57 (7): 2045-2053 (2022)A 97% Maximum Efficiency Fully Automated Control Turbo Boost Topology for Battery Chargers.B. Muniandi, C. Huang, C. Kuo, T. Yang, K. Chen, Y. Lin, S. Lin, and T. Tsai. IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (11): 4516-4527 (2019)A Hybrid Buck Converter Stacked on Auxiliary-switched-capacitor Using Analog and Digital Dynamic Voltage Scaling Techniques.T. Wu, Z. Shi-Jun, T. Wang, S. Lee, Y. Hsu, Y. Shih, J. Huang, K. Chen, K. Zheng, Y. Lin and 2 other author(s). ESSCIRC, page 429-432. IEEE, (2023)

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Disambiguation of "Lin, Ying-Hsi"

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A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS.

Please choose a person to relate this publication to

Ying Lin

Hsi-Lin Chao

Ying-Tung Lin

Ying Ying

Lin Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Ying-Hsi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS.

Please choose a person to relate this publication to

Ying Lin

Hsi-Lin Chao

Ying-Tung Lin

Ying Ying

Lin Lin

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS.