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Disambiguation of "Andersson, Oskar"

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A Neural Network Engine for Resource Constrained Embedded Systems.

, , , , and . ACSSC, page 125-131. IEEE, (2020)

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Magnus Oskarsson

Paul Andersson

Gunther Andersson

Christina Andersson

Olaf Anderßon

 

Other publications of authors with the same name

A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs., , , , , and . VLSI-SoC, page 380-385. IEEE, (2013)An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI., , , , and . A-SSCC, page 229-232. IEEE, (2016)A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks., , , and . ISCAS, page 1-5. IEEE, (2023)A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS., , , and . ESSCIRC, page 243-246. IEEE, (2014)Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS., , , , and . ESSCIRC, page 197-200. IEEE, (2013)Adaptive and multi-mode baseband systems for next generation wireless communication., , , , , , , and . ACSSC, page 1499-1503. IEEE, (2017)An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing., , , , , , and . VLSI-SoC (Selected Papers), volume 418 of IFIP Advances in Information and Communication Technology, page 88-106. Springer, (2012)Synthesis strategies for sub-VT systems., , , , and . ECCTD, page 552-555. IEEE, (2011)A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS., and . ISCAS, page 2628-2631. IEEE, (2015)A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI., , , , , and . ESSCIRC, page 429-432. IEEE, (2016)