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FPGA architecture characterization for system level performance analysis., , and . DATE, page 734-739. European Design and Automation Association, Leuven, Belgium, (2006)A Virtual File System for Dynamically Reconfigurable FPGAs., , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1127-1129. Springer, (2004)Transaction level modeling: flows and use models.. CODES+ISSS, page 75-80. ACM, (2004)Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry.. FPL, volume 1482 of Lecture Notes in Computer Science, page 199-208. Springer, (1998)From ESL 2010 to ESL 2015., , , , , and . CODES+ISSS, page 61-62. ACM, (2010)A dynamic reconfiguration run-time system., , , , and . FCCM, page 66-76. IEEE Computer Society, (1997)You can catch more bugs with transaction level honey., , , , , and . CODES+ISSS, page 121-124. ACM, (2008)SystemC for the Design and Modeling of Programmable Systems., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 811-820. Springer, (2004)Runtime Reconfigurable Routing., and . IPPS/SPDP Workshops, volume 1388 of Lecture Notes in Computer Science, page 25-30. Springer, (1998)Evaluation of SystemC Modelling of Reconfigurable Embedded Systems., , and . DATE, page 253-258. IEEE Computer Society, (2004)