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Disambiguation of "Jyo, Teruo"

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An over 220-GHz-Bandwidth Distributed Active Power Combiner in 250-nm InP DHBT.

, , , , , , and . BCICTS, page 1-4. IEEE, (2020)

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Nidhi Jyotsana

 

Other publications of authors with the same name

A DC-to-150-GHz InP-DHBT Active Combiner Module for Ultra-Broadband Signal Generation., , , , , and . BCICTS, page 195-198. IEEE, (2023)A 256-Gbps PAM-4 Signal Generator IC in 0.25-µm InP DHBT Technology., , , , , , and . BCICTS, page 28-31. IEEE, (2018)A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA., , and . RWS, page 217-219. IEEE, (2013)A 220-294 GHz Power Amplifier with 10-dBm Psat and 2.2% PAE in 250-nm InP DHBT., , , , , , , , , and . BCICTS, page 152-155. IEEE, (2022)110-GHz-Bandwidth InP-HBT AMUX/ADEMUX Circuits for Beyond-1-Tb/s/ch Digital Coherent Optical Transceivers., , , , , , , , , and 4 other author(s). CICC, page 1-8. IEEE, (2022)A Design of InP-HBT 100-GHz Diode Linearizer Toward 6G., , , , , , , and . APCC, page 140-144. IEEE, (2022)24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS., , , , , , , , , and 9 other author(s). ISSCC, page 415-417. IEEE, (2024)12.3 A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters., , , , and . ISSCC, page 212-214. IEEE, (2020)AMUX-based Bandwidth Tripler with Time-interleaved Nonlinear Digital Pre-distortion Enabling 216-GBd PS-PAM8 Signal., , , , , , , , , and 3 other author(s). OFC, page 1-3. IEEE, (2024)An over 220-GHz-Bandwidth Distributed Active Power Combiner in 250-nm InP DHBT., , , , , , and . BCICTS, page 1-4. IEEE, (2020)