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Disambiguation of "Simoglou, Stavros"

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Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance.

, , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (5): 962-972 (2021)

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Stavros Konstantinides

Stavros Kirkopoulos

Stavros Arabatzis

Stavros Vlizos

Stavros Bourlotos

 

Other publications of authors with the same name

Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (5): 962-972 (2021)STA for Mixed Cyclic, Acyclic Circuits., , , and . ISVLSI, page 392-397. IEEE, (2020)Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis., , , , , , , , and . DFT, page 1-6. IEEE, (2023)Timing Errors in STA-based Gate-Level Simulation., , and . ASYNC, page 1-2. IEEE, (2020)Abax: 2D/3D legaliser supporting look-ahead legalisation and blockage strategies., , and . DATE, page 1469-1472. IEEE, (2018)Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model., , , and . ISQED, page 1-8. IEEE, (2024)RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening., , and . DFT, page 1-6. IEEE, (2022)Graph-based STA for asynchronous controllers., , , and . Integr., (2020)Graph-Based STA for Asynchronous Controllers., , , and . PATMOS, page 9-16. IEEE, (2019)Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows., , , , and . VLSI-SoC, page 1-6. IEEE, (2022)