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Can a reconfigurable architecture beat ASIC as a CNN accelerator?, , and . SAMOS, page 97-104. IEEE, (2017)Reconfigurable Architecture for Base-band Data Processing., , and . PDPTA, CSREA Press, (2000)Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theorem., , , and . VLSI-SoC, page 60-65. IEEE, (2011)Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays., , and . J. Signal Process. Syst., 91 (5): 459-473 (2019)Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric., , , , , and . Microprocess. Microsystems, 38 (8): 788-802 (2014)Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures., , , , and . HEART, page 86-92. ACM, (2023)Design and Implementation of Optimized Register File for Streaming Applications., , , , , and . VDAT, page 1-4. IEEE, (2021)Clock Tree Generation by Abutment in Synchoros VLSI Design., , , and . NorCAS, page 1-7. IEEE, (2021)Scheduling Persistent and Fully Cooperative Instructions., , and . FCCM, page 274. IEEE, (2021)Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems., , and . FPL, volume 1142 of Lecture Notes in Computer Science, page 193-199. Springer, (1996)