( en | de | ru )

 

Disambiguation of "Kise, Kenji"

Author of the publication

copydeleteadd this publication to your clipboard
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs.

, , , and . NOCS, page 1-8. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Folma Kiser

Kenji Kurata

Kenji Kurata

Kenji Kamino

Thorleif Kiserud

 

Other publications of authors with the same name

ArchHDL: A Novel Hardware RTL Design Environment in C++., and . ARC, volume 9040 of Lecture Notes in Computer Science, page 53-64. Springer, (2015)ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs., , , , and . ARC, volume 7199 of Lecture Notes in Computer Science, page 138-150. Springer, (2012)Parallel Processing of Matrix Multiplication in a CPU and GPU Heterogeneous Environment., , , and . VECPAR, volume 4395 of Lecture Notes in Computer Science, page 305-318. Springer, (2006)SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator., , and . Asia-Pacific Computer Systems Architecture Conference, volume 2823 of Lecture Notes in Computer Science, page 122-136. Springer, (2003)A portable and Linux capable RISC-V computer system in Verilog HDL., , and . CoRR, (2020)Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs., , and . FPGA, page 211-221. ACM, (2020)A framework for efficient rapid prototyping by virtually enlarging FPGA resources., and . ReConFig, page 1-8. IEEE, (2014)Efficient Resource Shared RISC-V Multicore Processor., and . MCSoC, page 366-372. IEEE, (2021)A Challenge for an Efficient AMI-based Cache System on FPGA Soft Processors., , and . CANDAR, page 133-139. IEEE Computer Society, (2015)RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions., , and . CoRR, (2020)