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Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch.

, , , and . J. Signal Process. Syst., 51 (3): 257-268 (2008)

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Power-Aware Scheduling for Parallel Security Processors with Analytical Models., , , , , and . LCPC, volume 3602 of Lecture Notes in Computer Science, page 470-484. Springer, (2004)Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch., , , and . J. Signal Process. Syst., 51 (3): 257-268 (2008)PALF: compiler supports for irregular register files in clustered VLIW DSP processors., , and . Concurr. Comput. Pract. Exp., 19 (18): 2391-2406 (2007)Case Study: Support OpenCL Complex Class for Baseband Computing., , , and . IWOCL, page 23:1-23:2. ACM, (2019)Guest Editorial: Special Issue on Systems Optimizations for DSP and AI Applications., , and . J. Signal Process. Syst., 95 (5): 569-570 (May 2023)System-level design space exploration for security processor prototyping in analytical approaches., , and . ASP-DAC, page 376-380. ACM Press, (2005)An MILP-based wire spreading algorithm for PSM-aware layout modification., , and . ASP-DAC, page 364-369. IEEE, (2008)Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains., , , , , and . J. Supercomput., 42 (2): 201-223 (2007)Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores., , , , , , and . J. Signal Process. Syst., 51 (3): 269-288 (2008)Compiler Optimizations with DSP-Specific Semantic Descriptions., , and . LCPC, volume 2481 of Lecture Notes in Computer Science, page 75-89. Springer, (2002)