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Disambiguation of "Chielle, Eduardo"

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Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption.

, , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (6): 1924-1928 (June 2024)

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Eduardo Maurô

Eduardo Monari

Eduardo Ospina

Eduardo Klein

Eduardo Portabella

 

Other publications of authors with the same name

Efficient metric for register file criticality in processor-based systems., , , , and . LATW, page 1-6. IEEE, (2014)Real-time Private Membership Test using Homomorphic Encryption., , and . DATE, page 1282-1287. IEEE, (2021)Tuning software-based fault-tolerance techniques for power optimization., , and . PATMOS, page 1-7. IEEE, (2014)Experimental Applications on SRAM-Based FPGA for the NanosatC-BR2 Scientific Mission., , , , , , , and . IPDPS Workshops, page 140-146. IEEE, (2019)Coupling bit and modular arithmetic for efficient general-purpose fully homomorphic encryption., , , and . ACM Trans. Embed. Comput. Syst., 23 (4): 57:1-57:28 (July 2024)Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (6): 1924-1928 (June 2024)E3: A Framework for Compiling C++ Programs with Encrypted Operands., , , and . IACR Cryptology ePrint Archive, (2018)Designing and analyzing a SpaceWire router IP for soft errors detection., , , and . LATW, page 1-6. IEEE, (2011)CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution., , , , and . HOST, page 131-140. IEEE, (2019)Optimizing Ciphertext Management for Faster Fully Homomorphic Encryption Computation., , and . DATE, page 1-6. IEEE, (2024)