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A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing., , , , , and . SAMOS, volume 11733 of Lecture Notes in Computer Science, page 429-441. Springer, (2019)An In-DRAM Neural Network Processing Engine., , , , , , and . ISCAS, page 1-5. IEEE, (2019)A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces., , , , and . NewCAS, page 55-59. IEEE, (2024)Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node., , , , , , and . DATE, page 1083-1084. IEEE, (2022)Timing Analysis beyond Complementary CMOS Logic Styles., , , , and . ASPDAC, page 189-194. IEEE, (2024)Machine learning based soft error rate estimation of pass transistor logic in high-speed communication., , , , , , , and . ETS, page 1-4. IEEE, (2022)Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology., , , , , , and . ICECS 2022, page 1-4. IEEE, (2022)A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference., , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 367-380 (2022)