Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints., , , and . APCCAS, page 792-795. IEEE, (2006)VLSI block placement with alignment constraints based on corner block list., , , , and . ISCAS (6), page 6222-6225. IEEE, (2005)Evaluating a bounded slice-line grid assignment in O(nlogn) time., , , , , , and . ISCAS (4), page 708-711. IEEE, (2003)Buffer planning based on block exchanging., , , and . ISCAS, IEEE, (2006)A New Buffer Planning Algorithm Based on Room Resizing., , , and . EUC, volume 3824 of Lecture Notes in Computer Science, page 291-299. Springer, (2005)Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain., , , and . J. Comput. Sci. Technol., 20 (2): 224-230 (2005)Leakage power optimization for clock network using dual-Vth technology., , and . ISCAS, page 2769-2772. IEEE, (2008)Interconnect delay optimization via high level re-synthesis after floorplanning., , and . ISCAS (6), page 5641-5644. IEEE, (2005)Timing-driven global routing with efficient buffer insertion., , and . ISCAS (3), page 2449-2452. IEEE, (2005)Performance-Driven Steiner Tree Algorithm for Global Routing., , , , and . DAC, page 177-181. ACM Press, (1993)