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Disambiguation of "Cheng, Yuanqing"

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A body-biasing of readout circuit for STT-RAM with improved thermal reliability.

, , , , , and . ISCAS, page 1530-1533. IEEE, (2015)

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Yuanqing Gao

Yuanqing Guo

Cheng-Yung Cheng

I-Fen Cheng

Ying Min Cheng

 

Other publications of authors with the same name

Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength., , and . ACM Great Lakes Symposium on VLSI, page 399-404. ACM, (2020)AES design improvement towards information safety., , , , , , , and . ISCAS, page 1706-1709. IEEE, (2016)Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization., , , , , , , , , and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 30 (4): 440-448 (2022)PDG: A Prefetcher for Dynamic Graph Updating., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1246-1259 (April 2024)OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits., , , , and . ICCAD, page 1-9. IEEE, (2023)DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache., , , , and . ISQED, page 408-414. IEEE, (2020)ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY., , , , and . ICCAD, page 118. ACM, (2016)TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning., , , , , , and . DAC, page 1-6. IEEE, (2023)Quantitative evaluation of reliability and performance for STT-MRAM., , , , , , and . ISCAS, page 1150-1153. IEEE, (2016)Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (7): 2151-2162 (July 2024)