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Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (3): 482-489 (2010)Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model., , , and . J. Signal Process. Syst., 76 (2): 185-194 (2014)Design of a Low Power, Inductorless Wideband Variable-Gain Amplifier for High-Speed Receiver Systems., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (4): 696-707 (2012)A degree-matched check node approximation for LDPC decoding., , and . ISIT, page 1131-1135. IEEE, (2005)A 16-bit high-speed low-power hybrid adder., , , and . ICM, page 313-316. IEEE, (2016)Versatile Deep Learning Based Application for Time Series Imputation., , , , and . IJCNN, page 1-8. IEEE, (2021)On the Fault Tolerance of Stochastic Decoders., , and . ISMVL, page 219-223. IEEE Computer Society, (2017)A Tier 3 Software Defined AM Radio., , and . IWSOC, page 257-261. IEEE Computer Society, (2005)On Multiple Slice Turbo Codes., , , , and . Ann. des Télécommunications, 60 (1-2): 79-102 (2005)A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (1): 160-171 (2014)