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Architecture and synthesis for multi-cycle on-chip communication.

, , , , and . CODES+ISSS, page 77-78. ACM, (2003)

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Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (9): 986-997 (2006)Accelerating Sequential Applications on CMPs Using Core Spilling., , , , and . IEEE Trans. Parallel Distributed Syst., 18 (8): 1094-1107 (2007)Bitwidth-aware scheduling and binding in high-level synthesis., , , , , , and . ASP-DAC, page 856-861. ACM Press, (2005)Architecture and synthesis for on-chip multicycle communication., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (4): 550-564 (2004)Instruction set extension with shadow registers for configurable processors., , , , , and . FPGA, page 99-106. ACM, (2005)Architecture and compilation for data bandwidth improvement in configurable embedded processors., , and . ICCAD, page 263-270. IEEE Computer Society, (2005)Architecture and synthesis for multi-cycle on-chip communication., , , , and . CODES+ISSS, page 77-78. ACM, (2003)Application-specific instruction generation for configurable processor architectures., , , and . FPGA, page 183-189. ACM, (2004)Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication., , , , and . ICCAD, page 536-543. IEEE Computer Society / ACM, (2003)