Author of the publication

Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90nm CMOS process.

, , , and . EMBC, page 4485-4488. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Memory efficient architecture for belief propagation based disparity estimation., , , and . ISCAS, page 2521-2524. IEEE, (2015)23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications., , , , , and . ISSCC, page 1-3. IEEE, (2015)Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method., , and . APCCAS (1), page 363-366. IEEE, (2002)A VLSI architecture design of VLC encoder for high data rate video/image coding., , , and . ISCAS (4), page 398-401. IEEE, (1999)Low power full-search block-matching motion estimation chip for H.263+., , , and . ISCAS (4), page 299-302. IEEE, (1999)The Chip Design of A 32-b Logarithmic Number System., , and . ISCAS, page 167-170. IEEE, (1994)Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture., , and . ISCAS (2), page 273-276. IEEE, (2004)Low-cost hardware architecture design for 3D warping engine in multiview video applications., , and . ISCAS, page 2964-2967. IEEE, (2010)Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000., , , and . ISCAS (4), page 329-332. IEEE, (2002)Algorithm and hardware architecture design for weighted prediction in H.264/MPEG-4 AVC., , , and . ISCAS, IEEE, (2006)