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SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure.

Y. Han, X. Cheng, X. Xue, J. Han, J. Xu, and X. Zeng. IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1416-1420 (March 2024)

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Xue Xue Zhang

Xiaoyong Zhang

Xiaoyong Tian

Xiaoyong Zhang

Other publications of authors with the same name

A 9Mb HZO-Based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier.J. Yang, Q. Luo, X. Xue, H. Jiang, Q. Wu, Z. Han, Y. Cao, Y. Han, C. Dou, H. Lv and 2 other author(s). ISSCC, page 498-499. IEEE, (2023)Novel 15T SRAM Cell for Low Voltage High Reliability Application.Y. Han, Y. Zhao, Q. Hu, X. Liu, B. Peng, H. Jiang, J. Yang, and X. Xue. ASICON, page 1-4. IEEE, (2021)A 2Mb ReRAM with two bits error correction codes circuit for high reliability application.J. Yang, Y. Meng, X. Xue, R. Huang, Q. Zhou, J. Wu, and Y. Lin. ASICON, page 1-4. IEEE, (2013)Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications.Y. Cai, K. Zhou, X. Xue, M. Wang, and X. Zeng. ASICON, page 1-4. IEEE, (2019)A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications.L. Wu, C. Zhao, J. Wang, X. Yu, S. Chen, C. Li, J. Han, X. Xue, and X. Zeng. ASPDAC, page 551-556. IEEE, (2024)A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security.Y. Xie, X. Xue, J. Yang, Y. Lin, Q. Zou, R. Huang, and J. Wu. IEEE Trans. Circuits Syst. II Express Briefs, 63-II (4): 336-340 (2016)SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure.Y. Han, X. Cheng, X. Xue, J. Han, J. Xu, and X. Zeng. IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1416-1420 (March 2024)Branch and Bound for Sigmoid-Like Neural Network Verification.X. Xue, and M. Sun. ICFEM, volume 14308 of Lecture Notes in Computer Science, page 137-155. Springer, (2023)Arbitrary Style Transfer via Learning to Paint in the Feature Domain.Y. Huang, Y. Liu, M. e Jing, M. Wang, X. Xue, X. Zeng, and Y. Fan. ASICON, page 1-4. IEEE, (2021)Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS.Z. Guo, D. Chen, and X. Xue. ASICON, page 1-4. IEEE, (2021)

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Disambiguation of "Xue, Xiaoyong"

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SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure.

Please choose a person to relate this publication to

Xue Xue Zhang

Xiaoyong Zhang

Xiaoyong Tian

Xiaoyong Zhang

Xiaoyong Zhang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Xue, Xiaoyong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure.

Please choose a person to relate this publication to

Xue Xue Zhang

Xiaoyong Zhang

Xiaoyong Tian

Xiaoyong Zhang

Xiaoyong Zhang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure.