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Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits.

S. Houri, G. Billiot, M. Belleville, A. Valentian, and H. Fanet. RC, volume 9138 of Lecture Notes in Computer Science, page 267-272. Springer, (2015)

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Alexandre Darmoise

Alexandre Varnek

Alexandre Martins

Alexandre Alexeev

Alexandre Jousset

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An efficient metric of setup time for pulsed flip-flops based on output transition time.S. Bernard, A. Valentian, M. Belleville, D. Bol, and J. Legat. ICICDT, page 9-12. IEEE, (2013)UTBB FDSOI technology flexibility for ultra low power internet-of-things applications.E. Beigné, J. Christmann, A. Valentian, O. Billoint, E. Amat, and D. Morche. ESSDERC, page 164-167. IEEE, (2015)Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.E. Beigné, A. Valentian, B. Giraud, O. Thomas, T. Benoist, Y. Thonnart, S. Bernard, G. Moritz, O. Billoint, Y. Maneglia and 10 other author(s). DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Scalable Pitch-Constrained Neural Processing Unit for 3D Integration with Event-Based Imagers.M. Bouvier, A. Valentian, and G. Sicard. DAC, page 385-390. IEEE, (2021)The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators.B. Belhadj, A. Valentian, P. Vivet, M. Duranton, L. He, and O. Temam. CASES, page 1:1-1:9. ACM, (2014)Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits.L. Cadix, A. Farcy, C. Bermond, C. Fuchs, P. Leduc, M. Rousseau, M. Assous, A. Valentian, J. Roullard, E. Eid and 3 other author(s). 3DIC, page 1-7. IEEE, (2009)Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature.S. Bernard, M. Belleville, A. Valentian, J. Legat, and D. Bol. PATMOS, page 1-7. IEEE, (2014)Leveraging Sparsity with Spiking Recurrent Neural Networks for Energy-Efficient Keyword Spotting.M. Dampfhoffer, T. Mesquida, E. Hardy, A. Valentian, and L. Anghel. ICASSP, page 1-5. IEEE, (2023)Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction.Y. Thonnart, E. Beigné, A. Valentian, and P. Vivet. ASYNC, page 48-57. IEEE Computer Society, (2008)Overcoming the Data Deluge Challenges with Greener Electronics.J. Léquepeys, M. Duranton, S. Bonnetier, S. Catrou, R. Fournel, T. Ernst, L. Hérault, D. Louis, A. Jerraya, A. Valentian and 4 other author(s). ESSDERC, page 7-14. IEEE, (2021)

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Disambiguation of "Valentian, Alexandre"

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Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits.

Please choose a person to relate this publication to

Alexandre Darmoise

Alexandre Varnek

Alexandre Martins

Alexandre Alexeev

Alexandre Jousset

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Valentian, Alexandre"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits.

Please choose a person to relate this publication to

Alexandre Darmoise

Alexandre Varnek

Alexandre Martins

Alexandre Alexeev

Alexandre Jousset

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits.