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Secure extensions of FPGA soft core processors for symmetric key cryptography.

, , , and . ReCoSoC, page 1-8. IEEE, (2011)

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Contactless transmission of intellectual property data to protect FPGA designs., , and . VLSI-SoC, page 19-24. IEEE, (2015)Complete activation scheme for FPGA-oriented IP cores design protection., , , , , and . FPL, page 1. IEEE, (2017)The Security of ARM TrustZone in a FPGA-Based SoC., , and . IEEE Trans. Computers, 68 (8): 1238-1248 (2019)Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators., , and . IEEE Trans. Inf. Forensics Secur., 11 (6): 1291-1305 (2016)Security Assessment of Heterogeneous SoC-FPGA: On the Practicality of Cache Timing Attacks., and . VLSI-SoC, page 1-6. IEEE, (2021)Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level., , , , , , , , , and 1 other author(s). EuroS&P Workshops, page 96-102. IEEE, (2021)Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor., , and . HOST, page 81-84. IEEE, (2022)Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA., , , , and . HASP@ISCA, page 4. ACM, (2013)Functional Locking Modules for Design Protection of Intellectual Property Cores., and . FCCM, page 233. IEEE Computer Society, (2015)Targeting Tiled Architectures in Design Exploration., , , , , and . IPDPS, page 172. IEEE Computer Society, (2003)