Author of the publication

Dynamic Partitioned Global Address Spaces for power efficient DRAM virtualization.

, and . Green Computing Conference, page 485-492. IEEE Computer Society, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Centralized buffer router: A low latency, low power router for high radix NOCs., and . NOCS, page 1-8. IEEE, (2013)Algebraic Properties of some Parallel Processor Interconnection Networks., and . ICDE, page 611-618. IEEE Computer Society, (1984)Understanding Energy Aspects of Processing-near-Memory for HPC Workloads., , , and . MEMSYS, page 276-282. ACM, (2015)Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore., , and . MEMSYS, page 11-21. ACM, (2015)Using rapid prototyping in computer architecture design laboratories., , , and . WCAE@HPCA, page 4. ACM, (1996)Teaching Pipelining and Concurrency using Hardware Description Languages., , , , and . MSE, page 55-56. IEEE Computer Society, (1999)Dynamic Partitioned Global Address Spaces for power efficient DRAM virtualization., and . Green Computing Conference, page 485-492. IEEE Computer Society, (2010)Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory., , , , and . ISCA, page 380-392. IEEE Computer Society, (2016)Customizable Fault Tolerant Caches for Embedded Processors., and . ICCD, page 108-113. IEEE, (2006)Scouting: Fully Adaptive, Deadlock-Free Routing in Faulty Pipelined Networks., , , and . ICPADS, page 608-613. IEEE Computer Society, (1994)