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Disambiguation of "Lee, Jong Duk"

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Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme.

, , , , , , , , and . IEICE Trans. Electron., 91-C (5): 742-746 (2008)

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Duk Won Lee

Young Duk Lee

Duk Ho Lee

Duk-ho Lee

Duk-Yeon Lee

 

Other publications of authors with the same name

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)., , , , , , , and . IEICE Trans. Electron., 91-C (5): 731-735 (2008)Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)., , , , , and . IEICE Trans. Electron., 92-C (5): 620-626 (2009)Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices., , , , , , , and . IEICE Trans. Electron., 90-C (5): 988-993 (2007)Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory., , , , , and . IEICE Trans. Electron., 92-C (5): 659-663 (2009)Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers., , and . ISLPED, page 189-192. ACM, (2003)Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic., , , , , , , , and . ISMVL, page 267-272. IEEE Computer Society, (2003)Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme., , , , , , , , and . IEICE Trans. Electron., 91-C (5): 742-746 (2008)