( en | de | ru )

 

Disambiguation of "Höppner, Sebastian"

Author of the publication

copydeleteadd this publication to your clipboard
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.

, , , , , , , , , , , , , , , , , , , and . ISCAS, page 1. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Uta Höppner

Christa Höppner

Wilhelm Höppner

Hans Höppner

Herbert Höppner

 

Other publications of authors with the same name

Opportunities For A Hardware-Based OPC UA Server Implementation In Industry 4.0., , , , , , , , , and 3 other author(s). IECON, page 1-6. IEEE, (2021)A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power., , , , , , , , , and 7 other author(s). CICC, page 1-2. IEEE, (2023)Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip., , , , , , , , and . ARITH, page 37-44. IEEE, (2018)A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration., , , and . ISCAS, page 1-5. IEEE, (2019)A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM., , , , , , , , , and . COOL CHIPS, page 1-3. IEEE, (2020)Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System., , , , , , , , and . CoRR, (2019)Efficient Reward-Based Structural Plasticity on a SpiNNaker 2 Prototype., , , , , , , , , and . CoRR, (2019)A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI., , , , , , , , , and 3 other author(s). IEEE Trans. Biomed. Circuits Syst., 16 (1): 94-107 (2022)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 2973-2986 (2019)10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 188-189. IEEE, (2014)