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Disambiguation of "Zhan, Jing-Hong Conan"

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28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and.

, , , , , , , and . ISSCC, page 472-473. IEEE, (2014)

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Simon Conan

Zhan Kang

Zhan Gao

Yuanyuan Jing

Guangmei Jing

 

Other publications of authors with the same name

28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and., , , , , , , and . ISSCC, page 472-473. IEEE, (2014)A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE., , , and . ISSCC, page 200-201. IEEE, (2008)Analysis of emitter degenerated LC oscillators using bipolar technologies., , , and . ISCAS (1), page 669-672. IEEE, (2003)Session 20 overview: Frequency generation., and . ISSCC, page 344-345. IEEE, (2013)A 5 GHz, 21 dBm output-IP3 resistive feedback LNA in 90-nm CMOS., , , and . ESSCIRC, page 372-375. IEEE, (2007)10.4 A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax Transceiver with Integrated LNA, PA and T/R Switch Achieving +20dBm 1024-QAM MCS11 Pout and -43dB EVM Floor in 55nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 178-180. IEEE, (2020)A family of SiGe quadrature oscillators for microwave applications., , and . ISCAS (5), page 4891-4894. IEEE, (2005)Toward Automotive Surround-View Radars., , , , , , , , , and 21 other author(s). ISSCC, page 162-164. IEEE, (2019)An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability., , , and . CICC, page 749-752. IEEE, (2008)Full-rate injection-locked 10.3Gb/s clock and data recovery circuit in a 45GHz-fT SiGe process., , and . CICC, page 552-555. IEEE, (2005)