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Disambiguation of "Kousai, Shouhei"

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Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS.

, , , , and . IEEE J. Solid State Circuits, 50 (5): 1094-1106 (2015)

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A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC., , , , , , , , , and 2 other author(s). ISSCC, page 494-495. IEEE, (2013)Session 9 overview: Wireless transceiver techniques: Wireless subcommittee., and . ISSCC, page 160-161. IEEE, (2012)F5: Advanced RF CMOS transmitter techniques., , , , , and . ISSCC, page 1-2. IEEE, (2015)A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter., , , , , and . IEICE Trans. Electron., 95-C (6): 1008-1016 (2012)19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension., , , , , , , , , and 4 other author(s). ISSCC, page 330-331. IEEE, (2014)A 2.9mW, +/- 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibration., , , and . VLSIC, page 1-2. IEEE, (2014)An octave-range watt-level fully integrated CMOS switching power mixer array for linearization and back-off efficiency improvement., and . ISSCC, page 376-377. IEEE, (2009)A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations., , , , and . CICC, page 1-8. IEEE, (2014)A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations., , , , , , and . CICC, page 583-586. IEEE, (2005)Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology., , , and . A-SSCC, page 25-28. IEEE, (2016)