Author of the publication

An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter.

, , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (2): 434-442 (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current., , and . IEEE J. Solid State Circuits, 35 (10): 1498-1501 (2000)A Case Study for Improving Performances of Deep-Learning Processor with MRAM., , , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2024)Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks., , , , , and . IEICE Trans. Commun., 89-B (10): 2741-2751 (2006)A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture., , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3623-3633 (2006)A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2226-2233 (2012)STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier., , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (12): 2411-2417 (2014)Signal contributions to heavily diffusion-weighted functional magnetic resonance imaging investigated with multi-SE-EPI acquisitions., , , , , , , and . NeuroImage, (2014)7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2693-2700 (2011)Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure., , , , and . IEICE Trans. Electron., 95-C (10): 1675-1681 (2012)A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2701-2708 (2011)