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Performance Sensitivity of NUCA Caches to On-Chip Network Parameters., , , , and . SBAC-PAD, page 167-174. IEEE Computer Society, (2008)Analysis of static and dynamic energy consumption in NUCA caches: initial results., , , and . MEDEA@PACT, page 105-112. ACM, (2007)Industrial Challenge 2022: A High-Performance Real-Time Case Study on Arm., , , and . ECRTS, volume 231 of LIPIcs, page 1:1-1:15. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2022)The ARM scalable vector extension, , , , , , , , , and 1 other author(s). IEEE Micro, 37 (2): 26--39 (2017)Impact of on-chip network parameters on nuca cache performances., , , , and . IET Comput. Digit. Tech., 3 (5): 501-512 (2009)A power-efficient migration mechanism for D-NUCA caches., , , , and . DATE, page 598-601. IEEE, (2009)Performance and power optimizations for non-uniform cache memories.. University of Pisa, Italy, (2010)Loopapalooza: Investigating Limits of Loop-Level Parallelism with a Compiler-Driven Approach., , , and . ISPASS, page 128-138. IEEE, (2021)Leveraging Data Promotion for Low Power D-NUCA Caches., , , , , and . DSD, page 307-316. IEEE Computer Society, (2008)Speculative Vectorisation with Selective Replay., , and . ISCA, page 223-236. IEEE, (2021)