( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
The MosaicSim Simulator (Full Technical Report).

, , , , , , , , , и . CoRR, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Olivier Carloni

Luca Rizzini

Luca Tranchini

Luca Tuninetti

Alfonz Luca

 

Другие публикации лиц с тем же именем

Rialto: a bridge between description and implementation of control algorithms for wireless sensor networks., , и . EMSOFT, стр. 183-186. ACM, (2005)Photonic Network-on-Chip Design., , , , и . Integrated Circuits and Systems Springer, (2014)High-level synthesis of accelerators in embedded scalable platforms., , и . ASP-DAC, стр. 204-211. IEEE, (2016)Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead., , , , , , и . DATE, стр. 171-175. EDA Consortium San Jose, CA, USA / ACM DL, (2013)KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design., , и . FMCAD, стр. 105-109. IEEE, (2019)Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code., , , , , и . ICCD, стр. 129-137. IEEE, (2019)Machine-Learning-Based Microwave Sensing: A Case Study for the Food Industry., , , , , , , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (3): 503-514 (2021)Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (11): 3736-3747 (2020)Theory of latency-insensitive design., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (9): 1059-1076 (2001)Negative thinking in branch-and-bound: the case of unate covering., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (3): 281-294 (2000)