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Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance., , , , и . ACM Great Lakes Symposium on VLSI, стр. 77-83. ACM, (2022)Large scale circuit simulation exploiting combinatorial multigrid on massively parallel architectures., , и . MOCAST, стр. 1-4. IEEE, (2018)A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPU s., , и . SMACD, стр. 209-212. IEEE, (2018)A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects., , , и . SMACD, стр. 89-92. IEEE, (2019)Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models., , , , и . ASP-DAC, стр. 773-778. ACM, (2021)Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation., , , , и . ISQED, стр. 225-230. IEEE, (2020)Reduction of large-scale RLCk models via low-rank balanced truncation., , , и . CoRR, (2023)Heuristics to Augment the Performance of Tetris Legalization: Making a Fast but Inferior Method Competitive., , , , , , , и . J. Low Power Electron., 13 (2): 220-230 (2017)A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees Using Matrix Exponential., , , , и . ASP-DAC, стр. 1-6. ACM, (2023)Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential., , , , и . SMACD, стр. 1-4. IEEE, (2023)