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A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator., , и . ACM Great Lakes Symposium on VLSI, стр. 273-278. ACM, (2014)Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder., , и . ICECS, стр. 733-736. IEEE, (2002)A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders., , , , , , и . SiPS, стр. 288-293. IEEE, (2012)Bitwidth-aware high-level synthesis for designing low-power DSP applications., , , и . ICECS, стр. 531-534. IEEE, (2010)Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures., , , и . ICASSP, стр. 5036-5040. IEEE, (2014)Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system., , , и . EUSIPCO, стр. 1625-1629. IEEE, (2007)Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications., , , и . DASIP, том 14622 из Lecture Notes in Computer Science, стр. 83-95. Springer, (2024)A design methodology for IP integration., , и . ISCAS (4), стр. 711-714. IEEE, (2002)Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment., , , и . DATE, стр. 1118-1123. IEEE, (2019)Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis., , , , и . DATE, стр. 52-55. IEEE, (2021)