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Area and Delay Efficient Design of a Quantum Bit String Comparator.

, , , and . ISVLSI, page 51-56. IEEE Computer Society, (2017)

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An efficient approach for designing and minimizing reversible programmable logic arrays., , , and . ACM Great Lakes Symposium on VLSI, page 215-220. ACM, (2012)An efficient design technique of a quantum divider circuit., , and . ISCAS, page 2102-2105. IEEE, (2016)An optimal design of a fault tolerant reversible multiplier., , and . SoCC, page 37-42. IEEE, (2013)An IoT Based Smart System to Recommend Suitable Environment., , , and . ICRAI, page 163-167. ACM, (2020)An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder., , and . SoCC, page 98-103. IEEE, (2013)Realization of Reversible Logic in DNA Computing., , , , , , , and . BIBE, page 261-265. IEEE Computer Society, (2011)Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter., , , and . VLSI Design, page 103-108. IEEE Computer Society, (2013)Towards Designing Optimized Low Power Reversible Demultiplexer for Emerging Nanocircuits., and . SoCC, page 180-185. IEEE, (2018)An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem., , , , and . ISVLSI, page 116-121. IEEE Computer Society, (2017)Design and Implementation of a Reversible Central Processing Unit., and . ISVLSI, page 187-190. IEEE Computer Society, (2015)