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Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform.

, , , and . IAS, page 44-47. IEEE, (2010)

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1.8V 0.18µm CMOS Novel Successive Approximation ADC., , and . VLSI-SOC, page 375-379. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only)., and . FPGA, page 273. ACM, (2015)Evolutionary Cell Aided Design for Neural Network Architectures., , , and . CoRR, (2019)New Embedded Core Testing for System-on-Chips and System-in-Packages., and . CCECE, page 1897-1900. IEEE, (2006)Ballistic Deflection Transistors and the Emerging Nanoscale Era., , , , , and . ISCAS, page 61-64. IEEE, (2009)A Processor-In-Memory Architecture for Multimedia Compression., , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (4): 478-483 (2007)Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (7): 1327-1331 (2012)A New Test Methodology For DNL Error In Flash ADC's., , , and . DFT, page 582-590. IEEE Computer Society, (2005)A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test., and . ISVLSI, page 165-170. IEEE Computer Society, (2002)A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications., , , and . AHS, page 119-126. IEEE Computer Society, (2007)