Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" with reply.

V. Oklobdzija, H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko, and T. Sumi. IEEE J. Solid State Circuits, 32 (2): 292 (1997)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Nakase, Yasunobu

add a person with the name Nakase, Yasunobu

Other publications of authors with the same name

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" with reply.V. Oklobdzija, H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko, and T. Sumi. IEEE J. Solid State Circuits, 32 (2): 292 (1997)Design of a low power NoC router using Marching Memory Through type.R. Yasudo, T. Kagami, H. Amano, Y. Nakase, M. Watanabe, T. Oishi, T. Shimizu, and T. Nakamura. NOCS, page 111-118. IEEE, (2014)A 0.5V start-up 87% efficiency 0.75mm2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration.Y. Nakase, S. Hirose, H. Onoda, Y. Ido, Y. Shimizu, T. Oishi, T. Kumamoto, and T. Shimizu. CICC, page 1-4. IEEE, (2012)Authors Reply.H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, and K. Mashiko. IEEE J. Solid State Circuits, 32 (2): 293 (1997)Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface.Y. Nakase, Y. Morooka, D. Perlman, D. Kolor, J. Choi, H. Shin, T. Yoshimura, N. Watanabe, Y. Matsuda, M. Kumanoya and 1 other author(s). IEEE J. Solid State Circuits, 34 (4): 494-501 (1999)An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture.H. Makino, Y. Nakase, H. Suzuki, H. Morinaka, H. Shinohara, and K. Mashiko. IEEE J. Solid State Circuits, 31 (6): 773-783 (1996)Leading-zero anticipatory logic for high-speed floating point addition.H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko, and T. Sumi. IEEE J. Solid State Circuits, 31 (8): 1157-1164 (1996)A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree.N. Itoh, Y. Naemura, H. Makino, Y. Nakase, T. Yoshihara, and Y. Horiba. IEEE J. Solid State Circuits, 36 (2): 249-257 (2001)A low power NoC router using the marching memory through type.R. Yasudo, T. Kagami, H. Amano, Y. Nakase, M. Watanabe, T. Oishi, T. Shimizu, and T. Nakamura. COOL Chips, page 1-3. IEEE Computer Society, (2014)On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes.Y. Nakase, Y. Ido, T. Oishi, and T. Shimizu. IEICE Trans. Electron., 96-C (11): 1420-1427 (2013)

BibSonomy

Disambiguation of "Nakase, Yasunobu"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" with reply.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Nakase, Yasunobu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Comments on "Leading-zero anticipatory logic for high-speed floating point addition" with reply.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" with reply.