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Efficient algorithm for functional scheduling in hardware/software co-design., , и . FPT, стр. 65-72. IEEE, (2006)Efficient management of custom instructions for run-time reconfigurable instruction set processors., , и . FPT, стр. 261-264. IEEE, (2006)Partial rerouting algorithm for reconfigurable VLSI arrays., и . ISCAS (5), стр. 641-644. IEEE, (2003)A Hardware Efficient Technique for Rapid Lumen Segmentation from Endoscopic Images., , и . JCIS, стр. 716-719. JCIS / Association for Intelligent Machinery, Inc., (2002)Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits., , и . ISCAS, стр. 2628-2631. IEEE, (2014)Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays., , , и . ISCAS, стр. 2424-2427. IEEE, (2013)Instruction set customization for area-constrained FPGA designs., , , и . SoCC, стр. 329-334. IEEE, (2011)Residue-to-binary arithmetic converter for moduli set 2n -1, 2n, 2n+1, 2n+1 -1., , и . NSIP, стр. 185-188. Bogaziçi University Printhouse, (1999)Run-Time Computation and Communication Aware Mapping Heuristic for NoC-Based Heterogeneous MPSoC Platforms., , , и . PAAP, стр. 203-207. IEEE Computer Society, (2011)A Novel Approach for Multilevel Fixed Outline Floorplanning., , , и . PAAP, стр. 59-62. IEEE Computer Society, (2010)