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A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS.

Y. Fan, A. Kumar, T. Iwai, A. Roshan-Zamir, S. Cai, B. Sun, and S. Palermo. CICC, page 1-4. IEEE, (2019)

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Jian Cai

Yongjie Cai

Cai Berg

Lijun Cai

Cuifang Cai

Other publications of authors with the same name

A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS.S. Cai, E. Tabasy, A. Shafik, S. Kiran, S. Hoyos, and S. Palermo. VLSIC, page 158-. IEEE, (2015)Adaptively-tunable RF photonic filters.S. Cai, G. Choo, E. Tabasy, B. Wang, K. Entesari, and S. Palermo. MWSCAS, page 1-4. IEEE, (2015)A hardware accelerator for speech recognition applications.T. Chen, J. Zheng, X. Zhang, S. Cai, and Y. Chen. ASICON, page 760-763. IEEE, (2011)A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS.Y. Zhu, S. Cai, S. Kiran, Y. Fan, P. Chang, S. Hoyos, and S. Palermo. CICC, page 1-4. IEEE, (2020)A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS.S. Kiran, S. Cai, Y. Luo, S. Hoyos, and S. Palermo. IEEE J. Solid State Circuits, 54 (3): 659-671 (2019)A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS.Y. Fan, A. Kumar, T. Iwai, A. Roshan-Zamir, S. Cai, B. Sun, and S. Palermo. CICC, page 1-4. IEEE, (2019)Automated Tuning for Silicon Photonic Filters.K. Entesari, S. Palermo, C. Madsen, G. Choo, R. Rady, S. Cai, and B. Wang. OFC, page 1-3. IEEE, (2022)An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling.C. Chen, S. Cai, J. Xu, X. Zhu, F. Ye, and J. Ren. MWSCAS, page 1100-1103. IEEE, (2012)A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization.A. Shafik, E. Tabasy, S. Cai, K. Lee, S. Hoyos, and S. Palermo. IEEE J. Solid State Circuits, 51 (3): 671-685 (2016)3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS.A. Shafik, E. Tabasy, S. Cai, K. Lee, S. Hoyos, and S. Palermo. ISSCC, page 1-3. IEEE, (2015)

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Disambiguation of "Cai, Shengchang"

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A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS.

Please choose a person to relate this publication to

Jian Cai

Yongjie Cai

Cai Berg

Lijun Cai

Cuifang Cai

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cai, Shengchang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS.

Please choose a person to relate this publication to

Jian Cai

Yongjie Cai

Cai Berg

Lijun Cai

Cuifang Cai

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS.