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Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (10): 1226-1236 (1996)On determining sensitization criterion in an iterative gate sizing process., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (2): 231-238 (1999)Switching-activity driven gate sizing and Vth assignment for low power design., , и . ASP-DAC, стр. 576-581. IEEE, (2006)Architectural evaluations on TSV redundancy for reliability enhancement., , , и . DATE, стр. 566-571. IEEE, (2017)A bus architecture for crosstalk elimination in high performance processor design., , и . CODES+ISSS, стр. 247-252. ACM, (2006)New spare cell design for IR drop minimization in Engineering Change Order., , и . DAC, стр. 402-407. ACM, (2009)Thread-criticality aware dynamic cache reconfiguration in multi-core system., и . ICCAD, стр. 413-420. IEEE, (2013)Performance-driven interconnection optimization for microarchitecture synthesis., , , и . EURO-DAC, стр. 118-123. IEEE Computer Society Press, (1992)Multi-Level Logic Synthesis Using Communication Complexity., , и . DAC, стр. 215-220. ACM Press, (1989)Expanding In-Cone Obfuscated Tree for Anti SAT Attack., , , и . DATE, стр. 1-6. IEEE, (2023)