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Design time body bias selection for parametric yield improvement., , , and . ASP-DAC, page 681-688. IEEE, (2010)Edge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC., , , , , , , , and . ASP-DAC, page 295-296. IEEE, (2018)Derivation of signal flow for switch-level simulation., , , and . EURO-DAC, page 301-305. IEEE Computer Society, (1990)Ultra-low power circuit techniques for a new class of sub-mm3 sensor nodes., , , , and . CICC, page 1-8. IEEE, (2010)A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems., , and . CICC, page 397-400. IEEE, (2007)A 0.5V 2.2pW 2-transistor voltage reference., , , and . CICC, page 577-580. IEEE, (2009)Near-field communication using phase-locking and pulse signaling for millimeter-scale systems., , and . CICC, page 563-566. IEEE, (2009)Timing yield enhancement through soft edge flip-flop based design., , , , , , and . CICC, page 543-546. IEEE, (2008)A 5.8nW, 45ppm/°C on-chip CMOS wake-up timer using a constant charge subtraction scheme., , , and . CICC, page 1-4. IEEE, (2014)Mixed-signal stochastic computation demonstrated in an image sensor with integrated 2D edge detection and noise filtering., , , , and . CICC, page 1-4. IEEE, (2014)