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On the design of modulo 2n±1 residue generators., , , и . VLSI-SoC, стр. 33-38. IEEE, (2013)Efficient support vector machines implementation on Intel/Movidius Myriad 2., , , , , и . MOCAST, стр. 1-4. IEEE, (2018)A bit-interleaved systolic architecture for a high-speed RSA system., и . Integr., 30 (2): 169-175 (2001)On the Diminished-1 Modulo 2n+1 Addition and Subtraction., , и . J. Circuits Syst. Comput., 29 (5): 2030005:1-2030005:14 (2020)Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (4): 607-611 (2019)A segmentation-based BISR scheme., , , , и . ASP-DAC, стр. 652-657. IEEE, (2014)A radiation tolerant and self-repair memory cell., , , и . IOLTS, стр. 210-215. IEEE, (2013)Modulo 2n ± 1 Fused Add-Multiply Units., , , и . ISVLSI, стр. 91-96. IEEE Computer Society, (2015)High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures., , , и . ISVLSI, стр. 486-487. IEEE Computer Society, (2010)Efficient serial and parallel implementation of programmable fir filters based on the merging technique., , и . EUSIPCO, стр. 1-5. IEEE, (2008)