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Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip.

P. Chen, W. Liu, H. Chen, S. Li, M. Li, L. Yang, and N. Guan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (7): 1381-1394 (2021)

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Shiqing Fang

Shiqing Fan

Li Li

Other publications of authors with the same name

Meta-Learning for Natural Language Understanding under Continual Learning Framework.J. Wang, Y. Fan, D. Jiang, and S. Li. CoRR, (2020)EDLAB: A Benchmark for Edge Deep Learning Accelerators.H. Kong, S. Huai, D. Liu, L. Zhang, H. Chen, S. Zhu, S. Li, W. Liu, M. Rastogi, R. Subramaniam and 2 other author(s). IEEE Des. Test, 39 (3): 8-17 (2022)iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations.S. Zhu, S. Li, and W. Liu. ACM Great Lakes Symposium on VLSI, page 65-70. ACM, (2022)A 3D audio coding technique based on extracting the distance parameter.C. Yang, R. Hu, L. Su, W. Tu, X. Wang, Y. Yang, G. Gao, S. Dong, S. Wang, M. Zhang and 2 other author(s). ICME, page 1-6. IEEE Computer Society, (2014)A New Intelligent Trajectory Planning Algorithm Based on Bug2 Algorithm: Bridge Algorithm.S. Yang, X. Wang, Y. Wen, J. Wang, and S. Li. ROBIO, page 2079-2084. IEEE, (2019)Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip.P. Chen, W. Liu, H. Chen, S. Li, M. Li, L. Yang, and N. Guan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (7): 1381-1394 (2021)An Efficient Gustavson-Based Sparse Matrix-Matrix Multiplication Accelerator on Embedded FPGAs.S. Li, S. Huai, and W. Liu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (12): 4671-4680 (December 2023)Partial order based non-preemptive communication scheduling towards real-time networks-on-chip.P. Chen, H. Chen, J. Zhou, D. Liu, S. Li, W. Liu, W. Chang, and N. Guan. SAC, page 145-154. ACM, (2021)A Comprehensive Memory Management Framework for CPU-FPGA Heterogenous SoCs.Z. Du, Q. Zhang, M. Lin, S. Li, X. Li, and L. Ju. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (4): 1058-1071 (April 2023)NVM-Based FPGA Block RAM With Adaptive SLC-MLC Conversion.L. Ju, X. Sui, S. Li, M. Zhao, C. Xue, J. Hu, and Z. Jia. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (11): 2661-2672 (2018)

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Disambiguation of "Li, Shiqing"

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Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip.

Please choose a person to relate this publication to

Shiqing Fang

Shiqing Fan

Li Li

Li Li

Li Li

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Li, Shiqing"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip.

Please choose a person to relate this publication to

Shiqing Fang

Shiqing Fan

Li Li

Li Li

Li Li

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip.